vhdl others signal assignment

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(others => '-') in VHDL

I am trying to set res to "----" which is done in an example in my book. When I run the following code I get the message "failure1":

If I change

I do not get the errormessage.

I tried to isolate the problem and the following code does not give an error message:

But this did not give an error. So do you see why I get the errormessage in the first code?

• 2 \$\begingroup\$ "assert tb_res="----" report "failure1" .... Not sure what you are trying to achieve with this statement. You are literally asserting that "If tb result is not don't care, report it as a failure". Is this really what you need? \$\endgroup\$ –  Mitu Raj Commented Jun 26, 2022 at 14:54
• \$\begingroup\$ @MituRaj Yes, I am trying to find out why it works in one case, but not the other. \$\endgroup\$ –  user394334 Commented Jun 26, 2022 at 15:40
• \$\begingroup\$ It doesn't make any sense. You are comparing tb_res (value = doesn't care) with some number in right side, which is also doesn't care. You can't determine what would be the output of comparing two such values whose values can be anything. The result should hence be don't care as well. It won't be deterministic as you presume. \$\endgroup\$ –  Mitu Raj Commented Jun 26, 2022 at 17:39
• \$\begingroup\$ @MituRaj Thank you. I see, but why is it that it works in the second case? \$\endgroup\$ –  user394334 Commented Jun 26, 2022 at 18:21
• \$\begingroup\$ Because tb_res = 1111 is true for the stimulus you gave to DUT. So assertion is true, not a fail. \$\endgroup\$ –  Mitu Raj Commented Jun 26, 2022 at 18:39

2 Answers 2

You have a very subtle problem.

The short answer is, for this problem, do not use the package ieee.numeric_std_unsigned .

If you look in ieee.std_logic_1164 , you will find that it does not overload the implicitly defined = operator. Hence, matching will be character based - probably like you are expecting.

When you include ieee.numeric_std_unsigned , it treats '0' or 'L' as a '0', '1' or 'H' as a '1', and everything else as an 'X'. This is fine for RTL design, however, it is not so good for testbenches where you want to match on meta values. For ieee.numeric_std.unsigned it does the exact same thing.

For RTL, if you are really doing math, I recommend that you use ieee.numeric_std and types unsigned and signed.

With VHDL-2008, the language also introduces matching relationals, ?=, ?/=, ... . For equality, these treat - as don't care. Matching relationals also return std_ulogic values rather than boolean (when used with std_logic/std_ulogic).

For this reason, I now recommend that people use 'X' instead of '-'. For historical reasons, synthesis tools interpret either of these as a don't care. With the introduction of ?= , if you assign an output to "----" and then compare it with ?= to anything, the result is '1' (aka TRUE).

Hence, I recommend that you recode your when others as:

• 1 \$\begingroup\$ I normally use 'U' instead of 'X' for returns that should not be used. It makes no difference during synthesis, but lets me treat 'X' in the synthesis output as a warning rather than as an expected state. \$\endgroup\$ –  Simon Richter Commented Jun 28, 2022 at 18:22

I am pretty sure it is because it doesn't make sense to assign a Don't Care. Don't Care is a umbrella grouping that represents multiple valid, but distinct, values so it only makes sense as a comparison condition, not as a write value because you can only write one value.

It's like positive or negative numbers. Each represents a group of different distinct values so while it makes sense in a comparison to determine whether a value is part of the group or not, it doesn't make sense to assign the group itself to a single value. For example, if I tried to assign "all positive numbers" to an integer, that doesn't make any sense.

Besides, if you ever need to write a Don't Care, you might as well just write any distinct value to it. But even that is pointless: Just don't modify the register it at all. Just use the null keyword to do nothing.

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VHDL signal assignment with the OTHERS keyword

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

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Combining `others` expression with `signed` cast

Let var stand for a signed vector (library IEEE.NUMERIC_STD.ALL) of size m .

Let foo be another variable of type std_logic_vector(n-1 downto 0) , where n is smaller than m.

I want to concatenate a '0' left of foo , then pad it with zeroes in its right until it size is m and then store the result in var .

But Xilinx complains with the following message on synthesis:

How do I do what I want?

• 1 You haven't supplied the declaration for divisor, nor rdsor ,necessary to providing a solution. Note neither var nor foo appear in your one line snippet. You've also omitted which revision of the VHDL standard your tool expects. –  user1155120 Commented Nov 26, 2016 at 20:04

2 Answers 2

Assuming rdsor is equivalent to your theoretical var and divisor equivalent to foo you could use two assignments in a process statement:

This works because each element of rdsor is a separate signal and there is only one value for any particular time in a projected output waveform . By not providing an after time_expression in the waveform element of the second assignment the elements of rdsor slice will be assigned the second assignments expression values. (The elements of the first assignment are supplanted by the second). This method of overwriting the projected output waveform is commonly used in providing default values prior to incomplete condition coverage with if statements.

This example analyzes, elaborates and simulates, while doing nothing interesting it demonstrates index ranges are constructed properly.

Notice it avoids the issue of concatenation versus aggregation brought up by Matthew Taylor's answer.

For a single signal assignment in a method not sensitive to tool VHDL revision:

This uses concatenation and subsumes the others into an aggregate. There's a subtype declaration for the trailing '0's portion to allow the aggregate expression to be the target of a qualified expression.

This architecture also analyzes, elaborates and simulates proving index arithmetic is correct.

• Ups, I mixed up the names of the variables. Thank you for the exhaustive solution! –  Jsevillamol Commented Nov 26, 2016 at 22:37

You would need to use others as part of an aggregate not part of a concatenation . Here's a solution using an aggregate and attributes (which relies on you using VHDL 2008):

https://www.edaplayground.com/x/5Yuw

• Notice the -2008 option. –  user1155120 Commented Nov 26, 2016 at 21:42
• @user1155120 You're right. Not for the first time, I have inadvertently come up with a solution that requires VHDL 2008, because that switch is set by default for Riviera Pro on EDA Playground. –  Matthew Commented Nov 27, 2016 at 15:53

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Select Statement – VHDL Example

Assigning signals using selected signal assignment.

Select statements are used to assign signals in VHDL. They can only be used in combinational code outside of a process . A selected signal assignment is a clear way of assigning a signal based on a specific list of combinations for one input signal. The syntax is demonstrated in the example below. The signal name after with is the signal whose values are used to assign the output signal. The when others clause should always be used to avoid creating a latch by accident.

Note that if you try to put a select statement inside a process, you will get the error: Illegal sequential statement.

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Chapter 3 - Data Flow Descriptions

Section 6 - signal assignments.